Chip vendor introduces SSE5, help to simplify code, achieve greater efficiency for performance hungry apps.

Chip minnow AMD today announced it plans to update the x86 instruction set with new code for multimedia, security and high-performance computing applications.

SSE5 (5^th-generation Streaming SIMD Extensions) was originally developed by Intel for the Pentium III processor in 1999. The instruction set has since been expanded by both Intel and AMD and used in Pentium 4 and AMD Athlon processors.

SSE5 incorporates new three-operand commands that enable a single instruction to computer three variables by applying mathematical or logic function operations in one process. Previously, the limit had been two.

The other new feature is the Fused Multiply Accumulate (FMACxx) instruction. This allows a combination of multiplication and addition functions to be applied to three operands or variables to calculate iterative calculations with a single instruction.

AMD says the simplification of this process will enable high-speed execution of life-like graphics shading, fast photo rendering, spatialised audio effects and complex vector mathematics functions.

“Chip advancements and software improvements go hand-in-hand, to the benefit of consumers and enterprises alike,” said Phil Hester, senior vice president and chief technology officer, AMD. “The impact of our designs are best realized when AMD-based servers, PCs and devices enable software to more effectively solve every-day problems and enhance every-day experiences. By announcing our plans to add SSE5 instructions to the x86 instruction set ─ and by making the specification available today ─ we are enabling open and collaborative software innovation that will bring AMD’s advancements to life for our customers and end-users.”

AMD is also working with third-party vendors to get software development tools ready to make it easier to implement these new instructions in next-generation software.

“PGI's goal is to provide high-performance, cross-platform, production-quality parallel compilers and software development tools to the developer community,” said Douglas Miles, director, The Portland Group. “We are working closely with AMD to enable developers to quickly and easily leverage the SSE5 instruction set to enhance high performance computing, and the multi-core and multi-media capability of their software applications.”

The new specification has been released to the developer community and is available from AMD’s website at http://developer.amd.com/sse5.jsp. There’s no real hurry though – new hardware in the way of processors featuring SSE5 won’t arrive until AMD releases its “Bulldozer” core in 2009.